| General top/bottom-plate charge recycling technique for integrated switched capacitor DC-DC converters PC Lisboa, P Pérez-Nicoli, F Veirano, F Silveira IEEE Transactions on Circuits and Systems I: Regular Papers 63 (4), 470-481, 2016 | 30 | 2016 |
| Ultra low power pulse generator based on a ring oscillator with direct path current avoidance F Veirano, P Pérez, S Besio, P Castro, F Silveira 2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS), 1-4, 2013 | 25 | 2013 |
| A series–parallel switched capacitor step-up DC–DC converter and its gate-control circuits for over the supply rail switches P Pérez-Nicoli, PC Lisboa, F Veirano, F Silveira Analog Integrated Circuits and Signal Processing 85, 37-45, 2015 | 23 | 2015 |
| A compact lithium-ion battery charger for low-power applications P Pérez, F Veirano, F Silveira IEEE Transactions on Circuits and Systems II: Express Briefs 69 (3), 669-673, 2022 | 8 | 2022 |
| Low-power operational transconductance amplifier with slew-rate enhancement based on non-linear current mirror P Pérez-Nicoli, F Veirano, P Castro Lisboa, F Silveira Analog Integrated Circuits and Signal Processing 89, 521-529, 2016 | 8 | 2016 |
| High slew-rate OTA with low quiescent current based on non-linear current mirror P Pérez-Nicoli, F Veirano, PC Lisboa, F Silveira 2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2015 | 8 | 2015 |
| Design method for an ultra low power, low offset, symmetric OTA P Pérez-Nicoli, F Veirano, C Rossi-Aicardi, P Aguirre 2013 7th Argentine School of Micro-Nanoelectronics, Technology and …, 2013 | 8 | 2013 |
| Comparator with self controlled delay for active rectifiers in inductive powering P Pérez-Nicoli, F Veirano, F Silveira 2018 IEEE Wireless Power Transfer Conference (WPTC), 1-4, 2018 | 6 | 2018 |
| Optimum nMOS/pMOS imbalance for energy efficient digital circuits F Veirano, L Naviner, F Silveira IEEE Transactions on Circuits and Systems I: Regular Papers 64 (12), 3081-3091, 2017 | 6 | 2017 |
| Minimum operating voltage due to intrinsic noise in subthreshold digital logic in nanoscale CMOS F Veirano, F Silveira, L Naviner Journal of Low Power Electronics 12 (1), 74-81, 2016 | 6 | 2016 |
| Trends in volumetric-energy efficiency of implantable neurostimulators: a review from a circuits and systems perspective S Martínez, F Veirano, TG Constandinou, F Silveira IEEE Transactions on Biomedical Circuits and Systems 17 (1), 2-20, 2022 | 5 | 2022 |
| Analysis of stepwise charging limits and its implementation for efficiency improvement in switched capacitor DC–DC converters F Veirano, PC Lisboa, P Pérez-Nicoli, L Naviner, F Silveira Analog Integrated Circuits and Signal Processing, 1-12, 2021 | 5 | 2021 |
| DINABANG: explosive force hamstring rehabilitation biomechanics instrument D Santos, R Barboza, J Domínguez, A Fernández, F Veirano, P Pérez, ... Proceedings of the International Conference on Advances in Biomedicine and …, 2017 | 5 | 2017 |
| Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI F Veirano, L Naviner, F Silveira 2016 26th International Workshop on Power and Timing Modeling, Optimization …, 2016 | 5 | 2016 |
| Is intrinsic noise a limiting factor for subthreshold digital logic in nanoscale CMOS? F Veirano, F Silveira, L Navinery 2015 International Workshop on CMOS Variability (VARI), 45-50, 2015 | 4 | 2015 |
| Gate drive losses reduction in switched-capacitor DC-DC converters F Veirano, P Pérez-Nicoli, P Castro-Lisboa, F Silveira 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2018 | 3 | 2018 |
| A low cost system for self measurements of power consumption in field programmable gate arrays JP Oliver, F Veirano, D Bouvier, E Boemo Journal of Low Power Electronics 13 (1), 1-9, 2017 | 3 | 2017 |
| Asymmetrical length biasing for energy efficient digital circuits F Veirano, F Silveira, L Naviner 2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2017 | 3 | 2017 |
| Assistive technology: A multimodal interface to control PC mouse pointer and click S Bacelar, R Curiel, S Vanoli, MA Pérez, F Veirano, P Pérez-Nicoli 2021 IEEE URUCON, 278-281, 2021 | 1 | 2021 |
| Optimal asymmetrical back plane biasing for energy efficient digital circuits in 28 nm UTBB FD-SOI F Veirano, L Naviner, F Silveira Integration 65, 211-218, 2019 | 1 | 2019 |
