Design and implementation of time and frequency synchronization in LTE A Golnari, M Shabany, A Nezamalhosseini, G Gulak IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (12 …, 2015 | 44 | 2015 |
A Low Complexity Architecture for the Cell Search Applied to the LTE Systems A Golnari, G Sharifan, Y Amini, M Shabany 19th IEEE International Conference on Electronics, Circuits and Systems …, 2012 | 13 | 2012 |
Error-tolerant processors: Formal specification and verification A Golnari, Y Vizel, S Malik 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 286-293, 2015 | 11 | 2015 |
Evaluating matrix representations for error-tolerant computing PA Golnari, S Malik Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 4 | 2017 |
Sparse matrix to matrix multiplication: a representation and architecture for acceleration S Malik, PA Golnari 2019 IEEE 30th International Conference on Application-specific Systems …, 2019 | 1 | 2019 |
Sparse matrix to matrix multiplication: A representation and architecture for acceleration (long version) PA Golnari, S Malik arXiv preprint arXiv:1906.00327, 2019 | 1 | 2019 |
PPU: A control error-tolerant processor for streaming applications with formal guarantees PA Golnari, Y Yetim, M Martonosi, Y Vizel, S Malik ACM Journal on Emerging Technologies in Computing Systems (JETC) 13 (3), 1-29, 2017 | 1 | 2017 |
Transposition of left-hand-side operand to systolic matrix multiplication ML Hedlund, CA Clark, AE Phelps, TJ Norrie, S Honnavara-Prasad, ... US Patent 12,073,216, 2024 | | 2024 |
Multi-Modal Systolic Array For Matrix Multiplication ML Hedlund, CA Clark, AE Phelps, TJ Norrie, NP Jouppi, ... US Patent App. 18/168,972, 2024 | | 2024 |
Computing on Large, Sparse Datasets and Error-Prone Fabrics PA Golnari Princeton University, 2018 | | 2018 |